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Alif Semiconductor /AE722F80F55D5AS_CM55_HP_View /OSPI0 /OSPI_XIP_INCR_INST

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Interpret as OSPI_XIP_INCR_INST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INCR_INST

Description

OSPI XIP INCR Transfer Opcode Register

Fields

INCR_INST

XIP INCR transfer opcode. When OSPI_SPI_CTRLR0[XIP_INST_EN] bit is set to 1, OSPI sends instruction for all XIP transfers, this register field stores the instruction opcode to be sent when an INCR type transfer is requested on AHB bus. The number of bits to be send in instruction phase is determined by the OSPI_SPI_CTRLR0[INST_L] bit field.

Links

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Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data